Digital Signal Processing Reference
In-Depth Information
UP2,
UP1
Pin
Type
Pin Name
DE1
DE2
UP3
Function of Pin
Seven Segment Display 1
LED Segment E (0=on)
HEX1[4]
G3
AA24
21
Output
Seven Segment Display 1
LED Segment F (0=on)
HEX1[5]
D2
AA23
23
Output
Seven Segment Display 1
LED Segment G (0=on)
HEX1[6]
D1
AB24
24
Output
LCD_E
K3
50
Output
LCD Enable line
LCD_RW
K4
73
Output
LCD R/W control line
LCD_RS
K1
108
Output
LCD Register Select Line
LCD_DATA[0]
J1
94
Bidir.
LCD Data Bus
96
(133)
LCD_DATA[1]
J2
Bidir.
LCD Data Bus
LCD_DATA[2]
H1
98
Bidir.
LCD Data Bus
LCD_DATA[3]
H2
100
Bidir.
LCD Data Bus
102
(108)
LCD_DATA[4]
J4
Bidir.
LCD Data Bus
LCD_DATA[5]
J3
104
Bidir.
LCD Data Bus
LCD_DATA[6]
H4
106
Bidir.
LCD Data Bus
LCD_DATA[7]
H3
113
Bidir.
LCD Data Bus
PS2_CLK
H15
D26
12
30
Bidir.
PS2 Connector
PS2_DATA
J14
C24
13
31
Bidir.
PS2 Connector
153
48Mhz
91
25Mhz
50MHz Crystal Controlled
Clock
CLOCK
L1
N2
Input
VGA Red Video Signal
(highest bit)
VGA_RED
B7
E10
228
236
Output
VGA Green Video Signal
(highest bit)
VGA_GREEN
A8
D12
122
237
Output
VGA Blue Video Signal
(highest bit)
VGA_BLUE
B10
B12
170
238
Output
VGA Connector Vertical
Sync Signal
VGA_VSYNC
B11
D8
226
239
Output
VGA Connector Horizontal
Sync Signal
VGA_HSYNC
A11
A7
227
240
Output
The pushbuttons are not debounced on the UP3 and its clock frequency depends
on the board's JP3 jumper settings. Set JP3 to short pins 3-4 for the 48Mhz
clock. UP3 pins enclosed in parenthesis in table 2.4 are for the larger FPGA
used in the 1C12 version of the UP3 board. It requires more power and ground
pins so there are some minor pin differences.
On the UP2 board, the two pushbuttons are not debounced, the LEDs are the
seven segment decimal points, and its clock is 25Mhz. The original UP1 boards
look very similar to a UP2 and they use the same pin assignments as the UP2,
but they contain a smaller EPF10K20RC240 FPGA. Verify the part number on
the large FPGA chip on the right side of the board, if you are uncertain.
