FPGA Development Board Hardware and I/O Features - Rapid Prototyping of Digital Systems - page 50

Modern FPGAs are surface-mount chips that are soldered directly to the board.
It is difficult if not impossible to replace the FPGA chip without expensive
surface mount soldering equipment, so extreme care should be exercised when
interfacing the FPGA I/O pins to any external devices.
Standard I/O connector pin assignments used for external PS/2, serial, parallel,
VGA, network and USB I/O cables can be found in Appendix F.

Table 2.3 Requirements to use the different I/O Features

I/O Device Description Hardware Interface Needed

USB 1.1 Full Speed and Low Speed Processor & USB SIE engine core

Serial Port RS 232 Full Modem UART to send and receive data

Parallel Port IEEE 1284 State machine or Proc. for handshake

PS/2 Port PC Keyboard or Mouse Serial Data PS/2 state machine

VGA Port for
Video Display on
Monitor

RGB three 1bit signals on
UP1,2,3, 10bits on DE2
and 3bits on DE1

State machine for sync signals & user
logic to generate RGB color signals

IDE Port Connector on UP3 Processor & IDE Device Driver

Reset Switch Global Reset on UP3 Must use a reset in design

Pushbutton
Switches

debounced on DE1 & DE2
but not on the UP1,2, & 3

Most applications will need a switch
debounce Circuit on UP1,2,3

Expansion Cards Connect to .1 inch headers Depends on expansion card used

LEDs 1=ON (DE1 & DE2) None, but uses 1 FPGA I/O pin

LCD Display 16 Character by 2 line

ASCII Characters
on DE2& UP3

State machine or Processor to send
ASCII characters and LCD commands

I 2 C clock chip on UP3 Serial Data I 2 C state machine Real Time Clock

DIP/Slide Switch Switches (1=ON) None or Synchronizer Circuit

W HEN CONNECTING EXTERNAL HARDWARE , ADDITIONAL PINS ARE AVAILABLE FOR USE ON
THE HEADER CONNECTORS ON THE BOARD . F OR D ETAILS , REFER TO THE B OARD ' S
R EFERENCE M ANUAL , WHICH IS ON THE B OOK ' S DVD, AND IS ALSO AVAILABLE FREE AT
HTTP :// WWW . ALTERA . COM OR AT HTTP :// WWW . TERASIC . COM .

Also, remember to assign pins as shown in the tutorials to avoid randomly
turning on several of the memory devices at the same time. A tri-state bus
conflict occurs when several tri-state outputs are turned on and they attempt to
drive a single signal line to different logic levels. It is possible that such a tri-
state bus conflict on the memory data bus could damage the devices by
overheating after several minutes of operation.
Table 2.4 contains the pin assignments and names used for the DE1, DE2, UP3,
and UP2 board's most commonly used I/O devices that are used in basic digital
designs. A complete list of all pin assignments for all of the boards is too
lengthy to include here; however, they can be found in each of the FPGA
board's user manuals that are available on the topic's DVD in \ Board \Chap2.