Digital Signal Processing Reference
In-Depth Information
15.
Use the DFF part from the primitives storage library and enter the symbol in a schematic
using the graphical editor. Develop a simulation that exercises all of the features of the
D flip-flop. Use Help on DFF for more information on this primitive.
16.
Use the DFFE part from the primitives storage library and enter the symbol in a
schematic using the graphical editor. Develop a simulation that exercises all of the
features of the D flip-flop with a clock enable. Use Help on DFFE for more information
on this primitive.
17.
Use gates and a DFF part from the primitives storage library with graphical entry to
implement the state machine shown in the following state diagram. Verify correct
operation with a simulation using the Altera CAD tools. The simulation should exercise
all arcs in the state diagram. A and B are the two states, X is the output and Y is the
input. Use the timing analyzer's
Processing
Classic Timing Analyzer Tool
Registered performance
option tab to determine the maximum clock frequency on the
Cyclone device. Reset is asynchronous and the DFF Q output should be high for state B.
1
1
A
X = 0
B
X = 1
0
0
Reset
18.
Repeat the previous problem but use one-hot encoding on the state machine. For one-hot
encoding use two flip-flops with only one active for each state. For state A the flip-flop
outputs would be "10" and for state B "01". One-hot encoding is common in FPGAs.
