Digital Signal Processing Reference
In-Depth Information
orgat e
PB1
PB1
PB2
LED
PB2
inst
Figure 1.29
ORgate design symbol.
1.16 Functional Simulation
In large designs with long compile and simulation times, a faster
functional
simulation is commonly used initially. This type of simulation does not include
device delay times and it is used solely to check for logic errors. Although a
functional simulation is good for finding logic errors, a timing simulation is
still necessary to check for any timing related errors as illustrated earlier in the
tutorial.
Performing a Functional Simulation
To perform a functional simulation, set the simulator for functional simulation
with
Assignments
Settings.
Select
Simulator Settings
in the left column
and then change the simulation mode from Timing to
Functional
. Run
Processing
Generate Functional Simulation Netlist
. Finally, select
Processing
Start Simulation
. Open the Simulation Report waveform and
note that the output changes without any delay in response to an input, unlike
the earlier timing simulation. To switch back to a timing-mode simulation,
change the simulator setting back to timing, recompile, and restart the
simulation.
This short tutorial has gone through the basics of a simple design using a
common path through the design tools. As you continue to work with the tools,
you will want to explore more of the menus, options and shortcuts. Chapter 4
contains a tutorial that will introduce a more complex design example. In
Quartus II,
Help
Tu t o r i a l
also contains more tutorials. Quartus II video
tutorials and reference manuals are also available online at Altera's website,
www.altera.com
.
A number of files such as the *.q* files are maintained in the project directory
to support a design. Appendix B contains a list of different file extensions used
by Quartus II. One of the more important files in a project is the *.qsf file. It
contains the device type and pin assignments along with a number of other
project settings.
