Digital Signal Processing Reference
In-Depth Information
Before You Compile
Before you compile the Verilog code, the FPGA device type and pin numbers
need to be assigned with
Assignments
Device
and
Assignments
Pin
. If
your pins are already defined from the earlier Schematic Entry Tutorial, just
confirm the pin assignments. If you did not do this step earlier in the tutorial
see the device and pin assignment instructions at the end of Section 1.1.
Figure 1.25
Verilog active low OR-gate model (with syntax error).
At this point, Verilog code is generally ready to be compiled, simulated, and
downloaded to the board using steps identical to those used earlier in the
schematic entry method. Once pin assignments are made, they are stored in the
project's *.qsf file.
1.12 Compiling the Verilog Design
The Compile process checks for syntax errors, synthesizes the logic design,
produces timing information for simulation, fits the design on the FPGA, and
generates the file required to program the FPGA. After any changes are made
to the design files or pin assignments, the project should always be re-
compiled prior to simulation or programming.
Select
Project
ADD/Remove Files in Current Project
. Confirm that the
new
orgrate.v
file is now part of project and
remove
the tutorial's earlier
orgate.bdf
or
orgate.vhd
files that the new Verilog file replaces from the
project if either file is present. Click
OK
. Start the compiler with
Processing
Start Compilation
.
