Digital Signal Processing Reference
In-Depth Information
orgate.bdf
file that the new VHDL file replaces from the project's file list, if it
is present. Click
OK
. Start the compiler with
Processing
Start
Compilation
.
Checking for Compile Warnings and Errors
The project should compile with an error. After compiling the VHDL code, a
window indicating an error should appear. The result should look something
like Figure 1.22.
Double click on the first red error line and note that the cursor is placed in the
editor either on or after the line missing the semicolon (;). VHDL statements
should end with a semicolon. Add the semicolon to the end of the line so that it
is now reads:
LED <= NOT ( NOT PB1 OR NOT PB2 );
Now, recompile, and you should have no errors. You can simulate your VHDL
code using steps identical to the tutorial's earlier schematic version of the
project.
Viewing the Synthesized Logic in a Schematic
You can view the logic automatically generated by the VHDL synthesis tools
using
To o l s
Netlist Viewers
RTL Schematic,
after a successful
compilation. A schematic of the logic synthesized by your VHDL code will be
displayed as seen in Figure 1.23. This is a handy way to double check simple
logic designs when first becoming familiar with VHDL or Verilog hardware
description languages and their associated automatic logic synthesis tools.
Figure 1.23
Logic schematic that was automatically synthesized from the VHDL code.
