Digital Signal Processing Reference
In-Depth Information
Setting up the Architecture Body
Click the mouse at the bottom of the text field. (We will be inserting another
template here.) Following the earlier procedure for selecting a VHDL template
(start with a right click), select
VHDL
Constructs
Design
Units
Architecture Body
. (The
Architecture Body
specifies the internal
logic of the design.) The syntax for the
Architecture Body
appears in the text
window after the other text. (You can now see why the template is left
highlighted - had you not placed your cursor first, text would have appeared at
your last cursor position. If you do misplace the template, hitting the Edit
Undo key removes the new text.)
Editing the Architecture Body
Change the entity name in the
ARCHITECTURE
statement to
orgate
.
Template lines with a "--" preceding a comment, need to be edited
appropriately for each particular design. Delete the signal declaration line
since this simple design does not require internal signals. Delete the remaining
comment lines after BEGIN that start with "--", and insert
LED <= NOT (
NOT PB1 OR NOT PB2 )
as a single line. (This line contains a deliberate
syntax error that will be detected and fixed later.) Insert the following two
lines at the beginning of the text file to define the libraries for the
STD_LOGIC data type.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
This is the preferred data type for bits in VHDL. The file should now appear
similar to Figure 1.21.
Figure 1.21
VHDL OR-gate model (with syntax error).
