Digital Signal Processing Reference
In-Depth Information
To use a DHCP server to automatically configure the remaining network
settings, run the following commands:
ifconfig eth0 up
dhcpcd &
The command
ifconfig -a
will display the network settings. If a valid IP
address is displayed after the label
inet addr
, then the DE2 board is
successfully communicating on the network. To start any network server
services on the DE2 board, you must first run
inetd &
. Inetd is a server
daemon that monitors and manages all ports and internet services. Once the
inetd process is running, you can start one or more of the server services such
as
boa
(web server),
telnetd
(telnet server daemon), or
ftpd
(file transfer
protocol server daemon). Be sure to monitor the available memory as additional
processes are started.
A
LL
S
OURCE FILES FOR THIS
N
IOS
II
µ
C
LINUX
R
EFERENCE
D
ESIGN
CAN BE FOUND ON THE
DVD
IN THE
\DE
X
\C
HAP
18
D
IRECTORY
.
18.13 For additional information
This chapter has provided a brief overview of embedded operating and the port
of µClinux for the Nios II processor. Additional information about µClinux can
be found at the can be found at the official µClinux website (
www.uclinux.org
).
Additional information about the µClinux port for Nios II can be found at the
µClinux Wiki (
http://nioswiki.jot.com/WikiHome/
) and the Nios Community
forum (
http://www.niosforum.com
). More information about the other
embedded operating systems discussed in this chapter are available at
http://www.micrium.com/
,
http://ecos.sourceware.org/
,
http://www.rtos.com/
,
http://www.microtronix.com
,
http://www.mentor.com/
,
http://www.segger.com/
,
http://www.vector-informatik.de/
, and
http://www.euros-embedded.com/
.
18.14 Laboratory Exercises
1.
In Figure 18.4, notice that the clock frequency is set to 100 MHz. To handle the
computational needs of an operating systems, the clock rate was increased from the 50
MHz clock used in Chapter 17. Changing the clock frequency required several changes in
the PLL settings that generate the processor and memory clocks. Open the Quartus II
project for Chapter 18 that is provided on the DVD. What are the frequencies of the three
clock signals being generated by the PLL block? Why is the phase shift of the SDRAM
clock set to 108 degrees instead of the 54 degrees specified in Chapter 17?
