Tutorial IV: Nios II Processor Hardware Design - Rapid Prototyping of Digital Systems - page 367

file to add a component. In the Libraries pane of the Symbol dialog box,
expand the Project item and select the nios32 component. Click OK to add the
selected component. Click in the middle of schematic file to place your Nios
system.
17.16 Create a Phase-Locked Loop Component
SDRAM and the Nios II processor core operate on different clock edges. The
Nios processor uses the rising edge and SDRAM the falling edge. The SDRAM
would need a clock signal that is phase shifted by 180 degrees. An inverter
would do this, but the phase shift also needs to be adjusted a bit to correct for
the internal FPGA delays and the distance between the SDRAM and the FPGA
on the DE board. To create this SDRAM clock signal, a phase-locked loop
(PLL) component can be implemented on the FPGA. To create a PLL, use
Quartus II's MegaWizard Plug-in Manager by selecting To o l s MegaWizard
Plug-In Manager… . Click Next on page 1 of the wizard to create a new
component. On page 2, select the Installed Plug-Ins I/O ALTPLL module
from the list. Enter the full path of your project directory followed by the
filename up3_pll into the output filename field. Complete the remaining fields
with the information shown in Figure 17.16. Click Next to continue.
Figure 17.16 These are the initial settings for the ALTPLL module.
On page 3 of the MegaWizard manager, enter 50.00 MHz as the frequency of
the inclock0 input . Leave the other options set to their default values. Click
Next to continue. On page 4 of the MegaWizard manager, un-select all
checkmarks . Click Next twice to advance to page 6.
On page 6 of the MegaWizard manager, enter a Clock phase shift of -54 deg
(-3 ns). Leave the other options set to their default values. Click Finish to skip