Digital Signal Processing Reference
In-Depth Information
Figure 17.5
Nios II supports three different general configurations. Select Nios II/s for this tutorial.
Nios II processors can be compiled with support for one of four different
debugging systems. The differences between them are shown in Figure 17.6,
along with the FPGA resources required to implement each type of debugging.
There is an order of magnitude difference in the number of logic elements
required to implement Level 4 debugging versus Level 1 debugging. This
difference is significant when compared to the overall size of the Nios II
processor. The Level 4 debugging system is two to three times larger then the
Nios II/s processor itself. Since the cost of FPGAs are largely based on their
size, the debugging logic will typically be removed before a design enters
production to minimize the number of logic elements, and thus the size of the
FPGA, required for the production quantities.
The full features of Level 3 and Level 4 debugging are only available when a
license from First Silicon Solutions, a third-party company, is purchased. The
availability of this license within your company or school along with the
complexity of your end system and the size of the FPGA available will be the
primary factors in determining which debugging system should be selected for
