Digital Signal Processing Reference
In-Depth Information
17 Tutorial IV: Nios II Processor Hardware Design
Designing systems with embeddeded processors requires both hardware and
software design elements. A collection of CAD tools developed by Altera enable
you to design both the hardware and software for a fully functional,
customizable, soft-core processor called Nios II. This tutorial steps you through
the hardware implementation of a Nios II processor for the DE1 and DE2
boards, and Tutorial III (in the preceding chapter) introduces the software
design tools for the Nios II processor.
Upon completion of this tutorial, you will be able to:
•
Navigate Altera's SOPC Builder (Nios II processor design wizard),
•
Generate a custom Nios II processor core,
•
Create a PLL that supplies a clock signal for the on-board SDRAM, and
•
Specify the top-level pin assignments and project settings necessary for
implementing the Nios processor on the DE boards.
T
HE
DVD
CONTAINS A VERSION OF
C
HAPTERS
16
AND
17
FOR THE
UP 3
BOARDS
.
17.1 Install the DE board files
Run the installation program for Altera's University Program IP Library. This
program can be found on the DVD at
\Altera_Software\UP_IP_Library.exe
.
Figure 17.1
Import the default pin and project assignments for the DE board.
17.2 Creating a New Project
Create a new Quartus II project as illustrated in Tutorial I (see Section 1 of
Chapter 1). Use the project name
rpds17
and create a top-level Block
Diagram/Schematic file named
rpds17.bdf
.
