A RISC Design: Synthesis of the MIPS Processor Core - Rapid Prototyping of Digital Systems - page 308

After verifying correct operation with a simulation, download the design to the FPGA
board and trace execution of the program using the video output. Sort this four element
array 4, 3, 5, 1.
17. Add programmed keyboard input and video output to the sort program from the previous
problem using the keyboard, vga_sync, and char_rom FPGAcores. Use a dedicated
memory location to interface to I/O devices. Appendix A.36-38 of Computer
Organization and Design The Hardware/Software Interface contains an explanation of
MIPS memory-mapped terminal I/O.
18. The MIPS VHDL model was designed to be easy to understand. Investigate various
techniques to increase the clock rate such as using two dual-port memory blocks for the
register file, moving hardware to different pipeline stages to even out delays, or changing
the way memory is clocked. Additional fitter effort settings may also help. Use the timing
analysis tools to evaluate design changes.
19. Develop a VHDL synthesis model for another RISC processor's instruction set. Possible
choices include the Nios, Microblaze, Picoblaze, PowerPC, ARM, SUN SPARC, the
DEC ALPHA, and the HP PARISC. DVD Appendix D of Computer Organization and
Design The Hardware/Software Interface contains information on several RISC
processors. Earlier hardware implementations of the commercial RISC processors
designed before they became superscalar are more likely to fit on a FPGA.