Digital Signal Processing Reference
In-Depth Information
Set Unused Pins as Inputs
The memory chips on the development board could all be turned on at the
same time by unused pins on the FPGA, causing their tri-state output drivers to
try to force output data bus bits to different states. This causes high currents,
which can overheat and damage devices after several minutes. To eliminate the
possibility of any damage to the board, the following option should always be
set in a new project. On the menu bar, select
Assignments
Device
then
click
the
Device and Pin Options
button. Click on the
Unused Pins
tab and check
the
As inputs, tri-stated
option. Click
OK
and then
OK
in the first window.
This setting is saved in the projects *.qsf file. Any time you create a new
project repeat this step.
1.2 Compiling the Design
Compiling your design checks for syntax errors, synthesizes the logic design,
produces timing information for simulation, fits the design on the selected
FPGA, and generates the file required to download the program. After any
changes are made to the design files or pin assignments, the project will
always need to be re-compiled prior to simulation or downloading.
Compiling your Project
Compile by selecting
Processing
Start Compilation
. The compilation
report window will appear in the Quartus II screen and can be used to monitor
the compilation process, view warnings, and errors.
Checking for Compile Warnings and Errors
The project should compile with
0 Errors
. If a popup window appears that
states, "Full Compilation was Successful," then you have not made an error.
Info messages will appear in green in the message window. Warnings appear in
blue in the message window and Errors will be red. Errors must be corrected.
If you forget to assign pins, the compiler will select pins based on the best
performance for internal timing and routing. Since the pins for the pushbuttons
and the LED are pre-wired on the FPGA boards, their assignment cannot be
left up to the compiler and the user must always specify them.
Examining the Report File
After compilation, the compiler window shows a summary of the compiled
design including the FPGA logic and memory resources used by the design.
Select the
orgate.bdf
schematic window. Use
View
Show Location
Assignments
and check the schematic's I/O pins to verify the correct pin
numbers have been assigned. If a pin is not assigned you may have a typo
somewhere in one of the pin names or you did not save your pin assignments
earlier. You will need to recompile whenever you change pin assignments.
You can also check all of the FPGA's pins by going to the compiler report
window with
Processing
Compilation Report
, expanding the
Fitter file
folder
, and clicking on the
Pin-out file
.
