Digital Signal Processing Reference
In-Depth Information
The RECV_KBD process waits for a start bit, converts the next eight serial data
bits to parallel, stores the input character in the signal, charin, and sets a flag,
scan_ready, to indicate a new character was read. . The scan_ready or input
ready flag is a handshake signal needed to ensure that a new scan code is read
in and processed only once. Scan_ready is set whenever a new scan code is
received. The input signal, read, resets the scan ready handshake signal.
The process using this code to read the key scan code would need to wait until
the input ready flag, scan_ready, goes High. This process should then read in
the new scan code value, scan_code. Last, read should be forced High and Low
to clear the scan_ready handshake signal.
Since the set and reset conditions for scan_ready come from different processes
each with different clocks, it is necessary to write a third process to generate
the scan_ready handshake signal using the set and reset conditions from the
other two processes. Hitting a common key will send a 1-byte make code and a
2-byte break code. This will produce at least three different scan_code values
each time a key is hit and released.
A shift register is used with the filtered clock signals to perform the serial to
parallel conversion. No command is ever sent the keyboard and it powers up
using scan code set 2. Since commands are not sent to the keyboard, in this
example clock and data lines are not bi-directional. The parity bit is not
checked.
11.7 A Design Example Using the Keyboard FPGAcore
Here is a simple design using the Keyboard and LCD_Display FPGAcores. The
last six bytes of scan codes will appear in the LCD display (or on some FPGA
boards in the seven segment LEDs). The block code_FIFO saves the last six
scan codes for the LCD display and is not used on the FPGA boards with a two
digit hex LED display.
key board
VCC
key board_clk
key board_data
clock_48Mhz
reset
read
scan_code[7..0]
scan_ready
PS2_CLK
BIDIR
VCC
PS2_DATA
BIDIR
inst
code_FIFO
Hex_Display _Data[39..0]
scan_code[7..0]
scan_ready
clock_48Mhz
reset
Hex_display _data[39..0]
read
CLK_48Mhz
INPUT
VCC
inst3
LCD_Display
SW8
INPUT
OUTPUT
LCD_RS
reset
clk_48Mhz
Hex_Display _Data[num_hex_digits*41..0]
LCD_RS
LCD_E
LCD_RW
DATA_BUS[7..0]
VCC
OUTPUT
LCD_E
OUTPUT
VCC
LCD_RW
BIDIR
DATA_BUS[7..0]
Hex_Display _Data[39..0]
inst1
Figure 11.5
Example design using the Keyboard FPGAcore.
