Digital Signal Processing Reference
In-Depth Information
In Figure 11.1 the keyboard is sending a scan code of 16 for the "1" key and it
has a zero parity bit. When implementing the interface code, it will be
necessary to filter the slow keyboard clock to ensure reliable operation with the
fast logic inside the FPGA chip. Whenever an electrical pulse is transmitted on
a wire, electromagnetic properties of the wire cause the pulse to be distorted
and some portions of the pulse may be reflected from the end of the wire. On
some PS/2 keyboards and mice there is a reflected pulse on the cable that is
strong enough to cause additional phantom clocks to appear on the clock line.
Here is one approach that solves the reflected pulse problem. Feed the PS/2
clock signal into an 8-bit shift register that uses a 24MHz clock. AND the bits
of the shift register together and use the output of the AND gate as the new
"filtered" clock. This prevents noise and ringing on the clock line from causing
occasional extra clocks during the serial-to-parallel conversion in the FPGA
chip.
A few keyboards and mice will work without the clock filter and many will not.
They all will work with the clock filter, and it is relatively easy to implement.
This circuit is included in the FPGAcores for the keyboard and the mouse. Pin
assignments for the various FPGA boards are seen in Table 11.3
Table 11.3 The PS/2 Keyboard or Mouse Pin Assignments
Pin Name
DE1
DE2
UP3
UP2,
UP1
Pin
Type
Function of Pin
PS2_CLK
H15
D26
12
30
Bidir.
PS2 Connector
PS2_DATA
J14
C24
13
31
Bidir.
PS2 Connector
As seen in Figure 11.2, the computer system or FPGA chip in this case sends
commands to the PS/2 keyboard as follows:
1. System drives the clock line Low for approximately 60us to inhibit any new
keyboard data transmissions. The clock line is bi-directional.
2. System drives the data line Low and then releases the clock line to signal
that it has data for the keyboard.
3. The keyboard will generate clock signals in order to clock out the remaining
serial bits in the command.
4. The system will send its 8-bit command followed by a parity bit and a stop
bit.
5. After the stop bit is driven High, the data line is released.
Upon completion of each command byte, the keyboard will send an
acknowledge (ACK) signal, FA, if it received the data successfully. If the
system does not release the data line, the keyboard will continue to generate the
clock, and upon completion, it will send a 're-send command' signal, FE or FC,
to the system. A parity error or missing stop bit will also generate a re-send
command signal.
