Digital Signal Processing Reference
In-Depth Information
VGA_SY NC
INPUT
OUTPUT
Clock_48Mhz
VGA_Red
clock_48Mhz
red
green
blue
red_out
green_out
blue_out
horiz_sy nc_out
v ert _sy nc_out
v ideo_on
pixel_clock
pixel_row[ 9. . 0]
pixel_column[9..0]
VCC
OUTPUT
VGA_Green
OUTPUT
VCC
VGA_Blue
OUTPUT
VGA_HSy nc
OUTPUT
VGA_VSy nc
Pixel_row[ 9. . 0]
Pixel_column[9..0]
1
Char_ROM
clock
charact er_address[ 5. . 0]
f ont _row[ 2. . 0]
f ont _col[ 2. . 0]
rom_mux_out put
Pixel_row[ 9. . 4]
Pixel_row[ 3. . 1]
Pixel_column[3..1]
inst
Normally, more complex user designed logic is used to generate the character
address. The video example shown in Figure 10.8 is an implementation of the
MIPS RISC processor core. The values of major busses are displayed in
hexadecimal and it is possible to single step through instructions and watch the
values on the video display. This example includes both constant and variable
character display areas. The video setup is the same as the schematic, but
additional logic is used to generate the character address.
Figure 10.8
MIPS Computer Video Output.
