Digital Signal Processing Reference
In-Depth Information
END
IF
;
-- Put all video signals through DFFs to eliminate
-- any delays that can cause a blurry image
-- Turn off RGB outputs when outside video display area
red_out <= red
AND
video_on;
green_out <= green
AND
video_on;
blue_out <= blue
AND
video_on;
horiz_sync_out <= horiz_sync;
vert_sync_out <= vert_sync;
END
PROCESS
;
END
a;
To turn off RGB data when the pixels are not being displayed the video_on
signals are generated. Video_on is gated with the RGB inputs to produce the
RGB outputs. Video_on is low during the time that the beam is resetting to the
start of a new line or screen. They are used in the logic for the final RGB
outputs to force them to the zero state. VGA_SYNC also puts the all of video
outputs through a final register to eliminate any timing differences in the video
outputs. VGA_SYNC outputs the pixel row and column address. See the
comments at the end of VGA_SYNC.VHD for information on setting up other
screen resolutions and refresh rates.
10.5 Final Output Register for Video Signals
The final video output for the RGB and sync signals in any design should be
directly from a flip-flop output. Even a small time delay of a few nanoseconds
from the logic that generates the RGB color signals will cause a blurry video
image. Since the RGB signals must be delayed a pixel clock period to eliminate
any possible timing delays, the sync signals must also be delayed by clocking
them through a D flip-flop. If the outputs all come directly from a flip-flop
output, the video signals will all change at the same time and a sharper video
image is produced. The last few lines of VHDL code in the FPGAcore
VGA_SYNC design generate this final output register.
10.6 Required Pin Assignments for Video Output
The FPGA board requires the chip pins as seen in Table 10.1 to be defined in
the project's *.qsf file, or elsewhere in your design in order to display the video
signals. These pins are hard wired on the FPGA board to the VGA connector
and cannot be changed.
A pixel clock is also needed at the appropriate rate for the screen resolution and
refresh rate. A PLL is used to generate this clock on the FPGA. The FPGA's
external crystal controlled clock is used as input for the PLL on all boards
except the UP2 and UP1 (no PLL on these boards). On the UP3, set jumper JP3
to short pins 3-4 for the 48Mhz clock. A table of the common screen resolutions
and refresh rates with the required pixel clocks and sync counter values can be
found at the end of the VGA_SYNC IP core code.
