Digital Signal Processing Reference
In-Depth Information
Many VGA monitors will shut down if the two sync signals are not the correct
values. Most PC monitors have an LED that is green when it detects valid sync
signals and yellow when it does not lock in with the sync signals. Modern
monitors will sync up to an almost continuous range of refresh rates up to their
design maximum. In a PC graphics card, a dedicated video memory location is
used to store the color value of every pixel in the display. This memory is read
out as the beam scans across the screen to produce the RGB signals. There is
not enough memory inside current generation FPGA chips for this approach, so
other techniques will be developed which require less memory.
10.3 Using an FPGA for VGA Video Signal Generation
To provide interesting output options in complex designs, video output can be
developed using hardware inside the FPGA. Only five signals or pins are
required, two sync signals and three RGB color signals. A simple resistor and
diode circuit is used to convert TTL output pin signals from the FPGA to the
low voltage analog RGB signals for the video signal. This supports two levels
for each signal in the RGB data and thus produces a total of eight colors. This
circuit and a VGA connector for a monitor are already installed on the Altera
UP3 board. The FPGA's Phase Locked Loop (PLL) can be used to generate
clocks for a wide variety of video resolutions and refresh rates.
25 M hz
Clock
Horizontal
Sync
Sync G eneration
C ounters
Vertical
Sync
R ow C ol
VGA Signals
Data
from
Design
P ixel R A M or
C haracter
G enerator R O M
R
G
B
Figure 10.5
FPGA based generation of VGA Video Signals.
As seen in Figure 10.5, a 25.175 MHz clock, which is the 640 by 480 VGA
pixel data rate of approximately 40ns is used to drive counters that generate the
horizontal and vertical sync signals. Additional counters generate row and
column addresses. In some designs, pixel resolution will be reduced from 640
by 480 to a lower resolution by using a clock divide operation on the row and
column counters. The row and column addresses feed into a pixel RAM for
graphics data or a character generator ROM when used to display text. The
required RAM or ROM is also implemented inside the FPGA chip.
