Digital Signal Processing Reference
In-Depth Information
9.6 Simulation of the
Μ
P3 Computer
A simulation output from the VHDL model is seen in Figure 9.15. After a reset,
the test program seen in Figure 9.13, loads, adds, and stores a data value to
compute A = B + C. The final value is then loaded again to demonstrate that the
memory contains the correct value for A. The program then ends with a jump
instruction that jumps back to its own address producing an infinite loop. After
running the program, FF is stored in location 12. Memory can be examined in
the Simulator after running a program by clicking on the Logical Memories
section in the left column of the Simulation Report. An example is shown in
Figure 9.16. Note that the clock period is set to 20ns for simulation.
Figure 9.15
Simulation of the Simple ΜP 3 Computer Program.
Figure 9.16
Simulation display of ΜP 3 Computer Memory showing result stored in memory
