Digital Signal Processing Reference
In-Depth Information
STORE instruction starting at address 00. Data values for this example program
are stored in memory locations, 10, 11, and 12.
IR
00 00
ALU
register_AC
00 00
PC
00
+1
16
16
8
MAR
00
Memory
MW = '0'
00: 02 11
01:
00 12
02:
01 10
03:
03 03
10:
00 00
11:
00 04
12:
00 03
MDR
02 11
Figure 9.7
Datapath used for the ΜP 3 Computer Design after applying reset.
Consider the execution of the ADD machine instruction (0012) stored at
program location 01 in detail. The instruction, ADD
address
, adds the contents
of the memory location at address 12 to the contents of AC and stores the result
in AC. The following sequence of register transfer operations will be required
to fetch and execute this instruction.
FETCH
:
REGISTER TRANSFER CYCLE 1
:
MAR = PC prior to fetch
, read memory, IR = MDR, PC = PC + 1
First, the memory address register is loaded with the PC. In the example
program, the ADD instruction (0012) is at location 01 in memory, so the PC
and MAR will both contain 01. In this implementation of the computer, the
MAR=PC operation will be moved to the end of the fetch, decode, and execute
loop to the execute state in order to save a clock cycle. To fetch the instruction,
a memory read operation is started. After a small delay for the memory access
time, the ADD instruction is available at the input of the instruction register. To
set up for the next instruction fetch, one is added to the program counter. The
last two operations occur in parallel during one clock cycle using two different
data busses.
