Digital Signal Processing Reference
In-Depth Information
in red. On the DE1 and DE2, hit KEY2 once to start the train simulation
running. Hitting KEY2 again will stop the simulation. If you hit KEY2 twice
quickly while trains are stopped, it will single step to the next track sensor state
change. Other boards also use two pushbuttons for these functions.
Sensor and switch values are indicated with a green or red square on the
display. Switch values are the squares next to each switch location. Green
indicates no train present on a sensor and it indicates switch connected to
outside track for a switch.
On the DE2 and UP3 board's, the LCD display top line shows the values of the
sensor (s), and switch (sw) signals in binary and the bottom line indicates the
values of DirA and DirB in binary. The most significant bit in each field is the
highest numbered bit.
If a possible train wreck is detected by two trains running on the same track
segment, the simulation halts and the monitor will flash. The FPGA board's
slide or DIP switches control the speed of Train A (low 2 bits) and B (high 2
bits). Be sure to check operation with different train speeds. Many problems
occur more often with a fast moving and a slow moving train.
8.12 A Hardware Implementation of the Train System Layout
Using the new Digital Command Control (DCC) model trains
3
, a model train
system with a similar track layout and control scheme can be setup and
controlled by the FPGA board
4
. In DCC model trains, the train speed, direction,
and other special features are controlled via a bipolar bit stream that is
transmitted on the train tracks along with the power. A DCC decoder is located
inside each train's engine that interprets the DCC signals and initiates the
desired action (i.e., change in speed, direction, or feature status).
On a DCC system, trains are individually addressable. As seen in Figure 8.12,
the DCC signal's frequency or zero crossing rate is changed in the DCC signal
to transmit the data bits used for a command. A DCC command contains both a
train address and a speed command. Each train engine is assigned a unique
address. The electric motors in the train's engine are powered by a simple diode
circuit that provides full-wave rectification of the bipolar DCC signal that is
present on the track. In this way, the two metal train tracks can simultaneously
provide both direct current (DC) power and speed control commands for the
trains.
The output voltages and current levels provided by an FPGA output pin cannot
drive the DCC train signals directly, but an FPGA can send the DCC data
streams to the train track with the addition of a higher current H-bridge circuit
that controls the train's power supply. An H-bridge contains four large power
transistors that provide the higher drive current needed for DC motors and they
3
DCC standards are approved by the National Model Railroad Association and are available online
at
http://www.nmra.org/standards/DCC/standards_rps/DCCStds.html
.
4
Additional details on using FPGAs for DCC can be found in “Using the Using FPGAs to
Simulate and Implement Digital Design Systems in the Classroom”, by T. S. Hall and J. O.
Hamblen in the
Proceedings of the 2006 ASEE Southeast Section Conference
.
