State Machine Design: The Electric Train Controller - Rapid Prototyping of Digital Systems - page 162

8.10 Running the Train Control Simulation
Follow these steps to compile and simulate the state machine for the electric
train controller.
Select Current Project
Make Tcontrol.vhd the current project with File Open Project Name
Then find and select Tcontrol.vhd .
Compile and Simulate
Select Processing Start Compilation and Simulation . The simulator will
run automatically if there are no compile errors. Select
Processing Simulation Report to see the timing diagram display of your
simulation as seen in Figure 8.10. Whenever you change your VHDL (or
Verilog) source you will need to repeat this step. If you get compile errors,
clicking on the error will move the text editor to the error location. The Altera
software has extensive online help including HDL syntax examples.
Make any text changes to Tcontrol.vhd or Tcontrol.vwf (test vector waveform
file) with File Open . This brings up a special editor window. Note that the
menus at the top of the screen change depending on which window is currently
open.
Updating new Simulation Test Vectors
To update the simulation with new test vectors from a modified Tcontrol.vwf,
select Processing Start Simulation . The simulation will then run with the
new test vectors. If you modify Tcontrol.vhd, you will need to recompile first.
8.11 Running the Video Train System (After Successful
Simulation)
A simulated or "virtual" train system is provided to test the controller without
putting trains and people at risk. The simulation runs on the FPGA chip. The
output of the simulation is displayed on a VGA monitor connected directly to
the FPGA board. A typical video output display is seen in Figure 8.11. This
module is also written in VHDL and it provides the sensor inputs and uses the
outputs from the state machine to control the trains. The module tcontrol.vhd is
automatically connected to the train simulation.
Here are the steps to run the virtual train system simulation:
Select the top-level project
Make Train.vhd the current project with File Open Project Name
Then find and select Train.qpf . Train.qsf must be in the project directory since
it contains the FPGA chip pin assignment information needed for video outputs
and switch inputs. Double check that your FPGA Device type is correct.