Digital Signal Processing Reference
In-Depth Information
default:
begin
s w i t c h 1 = 0 ;
s w i t c h 2 = 0 ;
dirA = 2'b 00;
dirB = 2'b 00;
end
endcase
e n d
endmodule
8.8 Automatically Generating a State Diagram of a Design
You can use
To o l s
Netlist Viewers
State Diagram Viewer
to
automatically generate a state diagram and state table of a VHDL or Verilog
based state machine after it has been compiled successfully as seen in Figure
8.8. The encoding tab at the bottom will also display the state encodings which
typically use the one-hot encoding scheme (i.e., one flip-flop is used per state
and the active flip-flop indicates the current state).
Figure 8.8
Automatically generated state diagram of Tcontrol.vhd.
