Digital Signal Processing Reference
In-Depth Information
7.4 Verilog Synthesis Models of Gate Networks
The first example consists of a simple gate network. In this model, both a
concurrent assignment statement and a sequential always block are shown that
generate the same gate network. X is the output on one network and Y is the
output on the other gate network. The two gate networks operate in parallel.
In Verilog synthesis, inputs and outputs from the module will become I/O pins
on the programmable logic device. For comments “//” makes the rest of a line a
comment and “/*” and “*/” can be used to make a block of lines a comment.
The Quartus II editor performs syntax coloring and is useful to quickly find
major problems with Verilog syntax. Verilog is case sensitive just like C.
Verilog concurrent statements are executed in parallel. Inside an always
statement, statements are executed in sequential order, and all of the always
statements are executed in parallel. The
always
statement is Verilog's
equivalent of a
process
in VHDL.
A
A
B
C
B
C
X
Y
D(1)
D(2)
D(1)
D(2)
module
gatenetwork
(
A, B, C, D, X, Y
);
input
A
;
input
B
;
input
C
;
input [2:1]
D
;
output
X, Y
;
reg
Y
;
// concurrent assignment statement
wire
X
=
A
& ~(
B
|
C
) & (
D
[1] ^
D
[2]);
/* Always concurrent statement- sequential execution inside */
always @(
A
or
B
or
C
or
D
)
Y
=
A
& ~(
B
|
C
) & (
D
[1] ^
D
[2]);
endmodule
7.5 Verilog Synthesis Model of a Seven-segment LED Decoder
The following Verilog code implements a seven-segment decoder for seven-
segment LED displays. A 7-bit vector is used to assign the value of all seven
bits in a single case statement. In the 7-bit logic vector, the most-significant bit
is segment 'a' and the least-significant bit is segment 'g'. The logic synthesis
CAD tool automatically minimizes the logic required for implementation. The
signal Hex_digit contains the 4-bit binary value to be displayed in hexadecimal.
