Digital Signal Processing Reference
In-Depth Information
Depending on the synthesis tool settings, the states may be encoded or
constructed using the one-hot technique. Outputs are defined in the last
WITH… SELECT statement. This statement lists the output for each state and
eliminates possible problems with inferred latches. To avoid possible timing
problems, unsynchronized external inputs to a state machine should be
synchronized by passing them through one or two D flip-flops that are clocked
by the state machine's clock.
Re
s
et
A
0X
1X
X1
B
Output1
C
X0
Figure 6.1
State Diagram for st_mach VHDL example
LIBRARY
IEEE
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
ENTITY
st_mach
IS
PORT
( clk, reset
:
IN
STD_LOGIC
;
Input1, Input2
:
IN
STD_LOGIC
;
Output1
:
OUT
STD_LOGIC
);
END
st_mach;
ARCHITECTURE
A
OF
st_mach
IS
- - r t d t a e f r t t e
TYPE
STATE_TYPE
IS
( state_A, state_B, state_C );
SIGNAL
state: STATE_TYPE;
BEGIN
PROCESS
( reset, clk )
BEGIN
IF
reset = '1'
THEN
-- Reset State
state <= state_A;
ELSIF
clk
'EVENT
AND
clk = '1'
THEN
