Digital Signal Processing Reference
In-Depth Information
5.9 FPGAcore Mouse: Mouse Cursor
MOU S E
clock_48Mhz
clock_48Mhz
reset
mouse_dat a
mouse_dat a
mouse_clk
reset
mouse_clk
lef t _but t on
right_button
lef t _but t on
right_button
mouse_cursor_row[ 9. . 0]
mouse_cursor_row[ 9. . 0]
mouse_cursor_column[ 9. . 0]
mouse_cursor_column[ 9. . 0]
inst
Figure 5.9
Symbol for Mouse FPGAcore.
The FPGAcore Mouse shown in Figure 5.9 is used to read position data from a
mouse attached to the UP3's PS/2 connector. It outputs a row and column
cursor address for use in video applications. The mouse must be attached to the
FPGA board prior to downloading for proper initialization.
The internal operation of the core and more detailed information on mouse
applications, commands, and data formats can be found in Chapter 11.
5.9.1 VHDL Component Declaration
COMPONENT
mouse
PORT
( clock_48MHz, reset
:
IN
STD_LOGIC
;
mouse_data
:
INOUT
STD_LOGIC
;
mouse_clk
:
INOUT
STD_LOGIC
;
left_button, right_button :
OUT
STD_LOGIC
;
mouse_cursor_row
:
OUT
STD_LOGIC_VECTOR
( 9
DOWNTO
0 ) );
mouse_cursor_column
:
OUT
STD_LOGIC_VECTOR
( 9
DOWNTO
0 ) );
END
COMPONENT
;
5.9.2 Inputs
Clock_48MHz is an input pin that must be connected to the on-board clock. On
DE1 and DE2 boards a 50Mhz clock is used. Mouse_clk and mouse_data are
bi-directional PS/2 signal lines from the mouse.
