Digital Signal Processing Reference
In-Depth Information
5.2 FPGAcore DEC_7SEG: Hex to Seven-segment Decoder
Figure 5.2
Symbol for DEC_7SEG FPGAcore.
The FPGAcore Dec_7seg shown in Figure 5.2 is a hexadecimal to seven-
segment display decoder with active low outputs. This function is used to
display hex numbers on an FPGA board's seven-segment LED displays.
5.2.1 VHDL Component Declaration
COMPONENT
dec_7seg
PORT
( hex_digit
:
IN
STD_LOGIC_VECTOR
( 3
DOWNTO
0 );
seg_a, seg_b, seg_c,
seg_d, seg_e, seg_f,
seg_g
:
OUT
STD_LOGIC
);
END
COMPONENT
;
5.2.2 Inputs
Hex_digit is the 4-bit hexadecimal value to send to the LED display.
Hex_digit[3] is the most-significant bit.
5.2.3 Outputs
Segments a through g are active low and should be connected as output pins to
the corresponding pin on a seven-segment display. Table 5.3 lists the pin
assignments for the first two hex displays on the FPGA boards. The UP3 does
not contain seven segment displays, but it does have an LCD module. More
than two seven segment displays are available on both the DE1 and DE2
boards, see the appropriate board's user manuals for a complete list of pin
assignments.
