Digital Signal Processing Reference
In-Depth Information
5.1
FPGAcore LCD_Display: LCD Panel Character Display
LCD_Display
Hex_Display _Dat a[ num_hex_digit s*41. . 0]
Hex_Display _Dat a[ num_hex_digit s*41. . 0]
reset
LCD_RS
LCD_RS
LCD_E
reset
clk_48Mhz
LCD_E
LCD_RW
clk_48Mhz
LCD_RW
DATA_BUS[7..0]
DATA_BUS[7..0]
inst
Figure 5.1
Symbol for LCD_Display FPGAcore.
The LCD_Display core is used to display static ASCII characters and changing
hex values from hardware on the DE2's or UP3's 16 by 2 line LCD display
panel. The core's VHDL code can be configured internally by the user to
display different ASCII strings and hex data fields. Instructions can be found in
comments in the core's VHDL code. A Generic,
Num_Hex_Digits
, is used to set
the size of the Hex_Display_Data input (i.e., Each hex digit displayed requires
a 4-bit signal).
The LCD controller datasheet contains information on graphics characters and
LCD commands. A state machine is used to send data and commands to the
LCD controller and to generate the required handshake signals. An ASCII to
hex table can be found in Appendix D. See
LCD_Display.vhd
for more
information.
5.1.1 VHDL Component Declaration
COMPONENT
LCD_Display
PORT
(Hex_Display_Data:
IN STD_LOGIC_VECTOR
((Num_Hex_Digits*4)1
DOWNTO
0);
reset, clock_48MHz:
IN STD_LOGIC
;
LCD_RS, LCD_E:
OUT
STD_LOGIC
;
LCD_RW:
INOUT STD_LOGIC
;
DATA_BUS:
INOUT STD_LOGIC_VECTOR
(7
DOWNTO
0));
END
COMPONENT
;
5.1.2 Inputs
Hex_Display_Data contains the 4-bit hexadecimal hardware signal values to
convert to ASCII hex digits and send to the LED display. The Generic,
Num_Hex_Digits, adjusts the size of the input hex data. Generics can be
assigned a value in an HDL file or with a block's parameter assignment in a
schematic. In a schematic, use
View
Parameter assignment
to see the
generic value and the symbol's properties parameters tab to set it.
