FPGAcore Library Functions - Rapid Prototyping of Digital Systems - page 88

5 FPGAcore Library Functions
In complex hierarchical designs, intellectual property (IP) cores are frequently
used. An IP core is a previously developed synthesizable hardware design that
provides a widely used function. Commercially licensed IP cores include
functions such as microprocessors, microcontrollers, bus interfaces, multimedia
and DSP functions, and communications controllers. IP cores promote design
reuse and reduce development time by providing common hardware functions
for use in a new design.
The FPGAcore functions listed in Table 5.1 are designed to simplify use of the
FPGA board's pushbuttons, keyboard, mouse, LCD display, seven-segment
LEDs, and video output features. They can be used in schematic capture,
VHDL, or Verilog based designs. Full source code is provided on the DVD.

Table 5.1 The FPGAcore Functions.

FPGAcore
Name

Description

LCD_Display Displays ASCII Characters and Hex Data on an LCD Panel

DEC_7SEG Display Hex Data on a sevensegment LED Display

Debounce Pushbutton Debounce Circuit

OnePulse Pushbutton Single Pulse Circuit

Clk_Div Clock Prescaler with 7 slower frequency outputs (1MHz to 1hz)

VGA_Sync VGA Sync signal generator for FPGA that outputs pixel addresses

Video_PLL Used by VGA Sync to generate the video pixel clock using a PLL

Char_ROM Small Character Font ROM for video character generation

Keyboard Reads keyboard scan codes from the board's PS/2 connector

Mouse Reads PS/2 mouse data and outputs cursor row and column address

FPGAcores can be used as symbols from the FPGAcore library, accessed via a
VHDL package, or used as a component in other VHDL or Verilog files. An
example of using the FPGAcore package in VHDL can be found in the file
\ board \chap5\FPGApack.vhd available on the DVD. The use of FPGApack's
VHDL package saves retyping lengthy component declarations for the core
functions in each VHDL-based design.
This section contains a one-page summary of each FPGAcore interface. VHDL
source code is provided for all FPGAcores on the DVD. Additional
documentation, examples, and interface details can be found in later chapters
on video signal generation, the keyboard, and the mouse. The Clk_Div,
LCD_Display, and Debounce functions were already used in the tutorial design
example in Chapter 4.
For correct operation of the FPGAcore functions, I/O pin assignments must be
made as shown in the description of each FPGAcore function. Clock inputs are
also required on several of the FPGAcore functions. The Clk_Div FPGAcore is
setup to provide the slower clock signals needed by some of the core functions.