Digital Signal Processing Reference
In-Depth Information
11.
Using gates and the DFF part from the primitives/storage library, design a circuit that
implements the state machine shown below. Use two D flip-flops with an encoded state.
R
e
set
A
0X
1X
X1
B
Output1
C
X0
For the encoded states use A = "00", B = "01", and C = "10". Ensure that the undefined
"11" state enters a known state. Enter the design using the graphical editor. Develop a
simulation that tests the state machine for correct operation. The simulation should test
all states and arcs in the state diagram and the "11" state. Use the
Processing
Classic Timing Analyzer Tool
option to determine the maximum clock frequency
on the Cyclone device. Use an asynchronous reset.
12.
Repeat the previous problem using one-hot encoding. Recall that one-hot encoding uses
one flip-flop per state, and only one flip-flop is ever active at any given time in valid
states. The state encoding for the one-hot state machine would be A = "100", B = "010",
and C = "001". Start with a reset in the simulation. It is not necessary to test illegal states
in the one-hot simulation. One-hot state machine encoding is recommended by many
FPGA device manufacturers.
