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easy to make use of the parallelism of multiple cores. Such problems are
said to exhibit embarrassingly obvious parallelism and, although obvious,
this type of parallel computing application is very common. It is much
more difficult to get speed-up by parallelizing a single application and
then distributing the required computation over the multiple cores.
Figure 7.20 illustrates three common types of parallelism.
One challenging problem that chip designers now face is the prob-
lem of dark silicon . This is the fact that although we will be able to make
devices with many more transistors than today's chips, we will not be
able to power all of them simultaneously due to power density limita-
tions on the chip. Engineers are now actively looking for new ways
to reduce power consumption in their chip designs. Multicore chips -
requiring parallel programming - are therefore only a short-term solu-
tion to the problem of providing more performance per chip. In April
2005, Moore stated in an interview that it was clear that his law cannot be
sustained indefinitely:
Fig. 7.19. The Intel Xeon E7 processor contains
ten cores and a total of 2.6 billion transistors.
In terms of size [of transistors] you can see that we're approaching the size of
atoms which is a fundamental barrier, but it'll be two or three generations
before we get that far - but that's as far out as we've ever been able to see.
We have another 10 to 20 years before we reach a fundamental limit. By
then they'll be able to make bigger chips and have transistor budgets in the
billions. 16
Unless we can come up with some radically new processor technologies, the end
of Moore's law is in sight! In Chapter 15 we look at some possible solutions.
(a)
(b)
Mortar
(c)
Fig. 7.20. Parallel Computing Paradigms illustrated by Fox's wall construction analogy: (a) “pipeline”
parallelism, (b) “domain” parallelism, (c) “task” parallelism. (a) Pipeline parallelism in which each
bricklayer is responsible for laying one row of bricks. Obviously the bricklayer for the second row can-
not start until the first bricklayer has laid some bricks. Similarly, when the first bricklayer has finished
the top row of bricks, the others are still finishing. This is a good analogy for the parallelism used in
vector supercomputers (see section on supercomputers at the end of this chapter). (b) In domain par-
allelism, each bricklayer is responsible for a given section of the wall. Obviously at the edges of these
domains the two bricklayers need to coordinate their activity. This is a good analogy for the parallel-
ism used in distributed memory microprocessor-based parallel supercomputers. (c) Task parallelism is
where each bricklayer is free to collect a brick and put it anywhere in the wall. It is a good analogy for
the very common “embarrassingly obvious” parallelism of many types of application.
 
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