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times smaller, k times faster, and dissipate k 2 less power. IBM's MOS memory
chips had a feature size of five microns at the time. Dennard and his colleagues
projected shrinking the feature size to a fraction of a micron. The use of CMOS
technology has allowed IBM to shrink the minimum feature dimension to well
below 0.1 micron and enabled IBM to release the Power7 processor in 2010
with 1.2 billion transistors fabricated using a forty-five nanometer process
( Fig. 7.16 ).
As chips grew smaller, not only could more complex chips be designed
but also more of them could be produced on a single silicon wafer for the
same cost. Moore's law has now held true for nearly fifty years and has been
the engine for the vast growth in computing and information processing
devices. It was 1970 when Intel produced the first 1,024 bit (1 kilobit) DRAM
chip ( Fig. 7.17 ). Only a year later, the first microprocessor, the Intel 4004,
was produced with more than two thousand transistors etched in circuits ten
microns wide. Just twenty-five years later, in 1995, the industry was produc-
ing DRAM chips with sixty-four million bits (64 megabit) and microprocessors
like the Pentium with more than four million transistors and a minimum
feature size of 0.35 microns. By the turn of the millennium, the industry had
moved on to one thousand million bit (1 gigabit) DRAMs and to microproces-
sors such as the Pentium 4 with more than forty million transistors and a
minimum feature size of 0.18 microns. By 2010, the minimum feature size
was down to thirty-five nanometers and Intel, AMD, and Nvidia were produc-
ing chips with several billion transistors. There will soon be chips that are
capable of storing a hundred thousand million bits - more bits than there are
stars in our galaxy!
Powerful computers are now needed to design each new generation of chips:
literally, we are using our present-day computers to design the next generation
of computers. The international silicon industry produces the “Semiconductor
Roadmap” that examines the engineering and design challenges required to
keep on the track of Moore's law. Although the charts of the Semiconductor
Roadmap boldly carry forward Moore's law many years into the future, there
are many significant technical problems to be solved along the way. We will
look at some possible solutions in Chapter 15 .
Finally, in addition to these technical challenges, there is an economic
one: the sheer cost of building the manufacturing facility for each new gen-
eration of chips ( Fig. 7.18 ). Arthur Rock, one of the investors who helped
Moore and Noyce raise funding to start Intel, is credited with Rock's law,
which states: “A very small addendum to Moore's Law which says that the
cost of capital equipment to build semiconductors will double every four
years.” 13 It was this spiraling cost of fabrication facilities that led Morris
Chang, a Taiwanese engineer and entrepreneur, to pioneer the concept of
a silicon foundry - essentially a “fab-for-hire.” Companies can do their own
chip design and then pay the foundry to manufacture their chips. Chang set
up the Taiwan Semiconductor Manufacturing Company (TSMC) in 1987. It
is now the world's largest foundry with more than $13 billion in revenue.
According to James Plummer, Dean of the School of Engineering at Stanford
University:
Fig. 7.16. Scanning Electron Microscope
image of sub-100nm transistor devel-
oped at IBM.
Fig. 7.17. Intel's revolutionary 1103
memory chip. One of the first custom-
ers was Xerox PARC where Chuck
Thacker and Butler Lampson used the
temperamental chip for the memory of
famous Alto personal computer (see next
chapter).
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