Models for Delay Faults - Models in Hardware Testing - page 85

Tabl e 3. 3 TDFs detected by
pseudo-functional tests

Circuit # Det-pseudo # Det-arb

S3330 3,302 3,937

S5378 5,404 6,412

S9234 4,819 9,505

S13207 9,658 12,489

S15850 11,738 13,535

S38417 46,926 48,761

S35932 54,599 54,599

S38584 53,349 55,123

Fig. 3.14 A sequential
circuit with STR fault et al.

b×01

c 0 0 1/0

a1

011

PO

a

0 1/0 1/0

×01

a2
011

FF

by pseudo-functional tests is that even though in general LOS tests detect more
faults than LOC (broadside) tests many faults that are detected by functional and
pseudo-functional tests are not detected by LOS tests ( Zhang et al. 2007 a). Thus
LOS tests may cause test escapes that cause malfunction of circuits in normal
operation.

3.2.3 Tests with Multiple Activation Cycles

Tests to detect delay faults described so far used one launch cycle and one capture
cycle. The launch cycle activates and propagates the fault. However some delay
faults require multiple activation cycles for detection ( Brand et al. 1994 , Zhang
et al. 2006 a , Abraham et al. 2006 ). This is illustrated using an example from Zhang
et al. ( 2006 a).
Consider the sequential circuit shown in Fig. 3.14 . Assume a slow to rise (STR)
TDF on line a1. By definition a transition fault represents a delay fault of large
(infinite) size. Consider a sequence of inputs 011 applied to a in three consecutive
clock cycles. The values on all the signal lines in the circuit are shown using the
standard notation of p/q to represent fault-free/faulty values on a signal line. It can
be seen that the TDF on a1 affects the circuit performance in the sense that in its
presence the circuit malfunctions when the input sequence 011 is applied. Now
consider generating a test to detect the STR fault on a1 using a standard single
activation cycle LOC test. Generation of such tests use an iterative logic array of two
time frames as illustrated in Fig. 3.15 a . Clearly the STR fault at a1 is not detectable
since the fault effect is not propagated to the primary output or the flip-flop. A three
cycles test, which uses an ILA of three time frames, is illustrated in Fig. 3.15 b .