Models for Delay Faults - Models in Hardware Testing - page 82

Resistive interconnect opens are one cause for delay defects. Noting that a re-
sistive open slows down both the rising and falling transition on the defective line,
Inline Resistance Fault model was proposed in Benware et al. ( 2004 ). An inline
resistance fault on line r is detected if either a slow to rise or a slow to fall fault
is detected on line r . Inline resistance fault model allows reduction in test patterns
compared to TDF fault model.
When determining TDF coverage by a given sequence for a non-scan sequential
circuit it is necessary to consider persistence of fault effects over more than one
clock cycle ( Cheng 1993 ) . This requires simulating the sequence several times with
different numbers of fault effect persistence cycles. In Pomeranz et al. ( 2008 b) a
transition delay fault model called Unspecified Transition Fault model was proposed
which allows a one pass simulation of the given sequence.

3.2 Test Generation for TDFs and Small Delay Defects

In delay fault testing two conflicting goals need to be considered. One is achieving
as high defect coverage as possible and the other is to avoid over testing. Over
testing occurs due to non-functional operation during scan based test application
( Rearick 2001 ). In this section we review some of the recent works related to both
these issues.
As discussed above defects that increase circuit delays are modeled by gate de-
lay faults, transition delay faults (TDFs) and path delay faults. Application of tests
to detect all path delay faults is impractical and gate delay faults require accurate
timing models. For these reasons for the detection of delay defects in industrial de-
signs typically tests for TDFs are used together with tests for selected critical paths.
However tests for TDFs may not provide adequate coverage of delay defects that
are of small size. This can be seen by the example in Fig. 3.13 . A TDF on line a
can be propagated either through path a-f-g-j or through a-f-k. Typically test pat-
tern generation tools propagate tests through easier to sensitize paths and hence the

d

g

j

a
b

f

X

h

e

k

c

Fig. 3.13 Gate delay faults