Models for Delay Faults - Models in Hardware Testing - page 81

avoid (b,f) pairs of lines and such that the subset contains at least one path delay
fault for each circuit lead with maximum delay among all paths containing the lead.
Over 90% of the path delay faults in such subsets were found to be testable.

3.1.6 Additional Delay Fault Models

In addition to the basic delay fault models, gate and path delay faults, several other
fault models have been proposed. These include double and multiple transition fault
model ( Pomeranz et al. 1996b ) and the segment fault model ( Heragu et al. 1996 ) .
These fault models require tests that robustly propagate transitions through subpaths
containing pairs or multiple lines of circuits. Segment fault model considers a set
of two or more consecutive circuit lines. These fault models are more complex than
TDF model but are less demanding than path delay fault model.
Even though path delay faults model the effect of accumulated delays along the
circuit lines on the path a non-robust test for a path delay fault may not detect ex-
tra delay in a lead or a subpath of the path. This is illustrated in Fig. 3.12 . Thetwo
pattern test shown in Fig. 3.12 is a non-robust test for the path b-d-f with a rising
transition at b. However, this test does not detect the STR fault on line b as shown by
the faulty circuit values under “/”. This means that if the circuit shown in Fig. 3.12
is part of a larger circuit a non-robust test for a path that contains the subpath b-d-f
may not detect accumulated excess delay up to line b. Given that many if not most
of the path delay faults can only be detected by non-robust tests, methods to gener-
ate non-robust tests to address this weakness were investigated. Towards this goal,
in Pomeranz et al. ( 2008 a) a fault model called Transition Path Delay Faults was
proposed. This model requires that a test that detects a path delay fault also detects
appropriate transition delay faults on each on-path line.
In many designs handcrafted custom blocks are used for which accurate or even
any gate level descriptions may not be available. Tests for delay faults for such de-
signs need to consider them as black boxes. For such designs functional test methods
were proposed in Underwood et al. ( 1994 ) and Pomeranz et al. ( 1995 a ).

X1

a

d 1 0/1

f 1 0

0 1/0

b

X

e

1 0

1 1/0

c

Fig. 3.12 Invalidation of a non-robust test