Models for Delay Faults - Models in Hardware Testing - page 74

and falling transitions, respectively, on the circuit lead. Path delay faults model in-
creases from the modeled delay for the logical paths and hence include the sum of
delay increases, if any, anywhere along the path. In a circuit with N lines there are
2 N single gate delay faults. However one needs to consider a range of delay de-
fect sizes which makes this model more complex than is indicated by the number of
faults. Since there could be exponentially large number of paths in a circuit the total
number of path delay faults in a circuit could be extremely large. For this reason a
fault model called transition delay fault (TDF) or simply transition fault has been
proposed ( Barzilai et al. 1983 ) . In this model, as in the gate delay fault model, we
associate with each circuit line an STF and an STR fault and assume that the defect
size is so large that every signal path containing the defect site has a delay higher
than the delay permitted by the test clock period ( Waicukauski et al. 1987 ).

3.1.3 Tests to Detect Delay Faults

Methods to generate tests to detect delay faults use the basic steps described in
Section 3.1.1 . Test generation and fault simulation methods for combinational cir-
cuits and scan designs as well as for sequential circuits have been investigated. First
some basic procedures are reviewed using combinational circuit examples followed
by a short review of work on sequential circuits.
Tests for TDFs can be generated by straight forward modification of procedures
for generating tests to detect line stuck-at faults ( Waicukauski et al. 1987 ) . For ex-
ample consider detection of an STR fault on line d in the circuit shown in Fig. 3.3 .
In order to activate this fault we should create a rising transition on line d .This
implies that the fault can only be activated by applying two consecutive patterns.
A pair of such patterns is shown in Fig. 3.3 a . In the presence of an STR fault on line
d the value on d will not change to 1 from 0 before the circuit outputs are read due
to the assumption that the delay defect size is large enough. Thus when the circuit
output is read, line d will still be 0. This is shown as the faulty value under the slash
in Fig. 3.3 b . Thus the STR TDF manifests itself as a stuck-at-0 fault when the sec-
ond input of the two pattern test is applied. In general, to detect a STR(STF) TDF
a two pattern test <t1,t2> must satisfy the following two conditions: (i) the first

a b

a a

d 01 d 0 1/0

11 11

f 10 f 10/1

b b

10 10

e 11 e

11

c c

00 00

Fig. 3.3 Illustrating detection of an STR fault