Hardware Reference
In-Depth Information
0
a
b
f
0/1
j
X
1/0
0
m
1/0
0
c
d
g
0
0
k
0
e
1
Fig. 3.2
Detecting line f stuck-at-1
A stuck-at-0(1) fault on line r is activated by setting line r to 1(0) in the fault-free
circuit. Note that in the faulty circuit, line r remains at the stuck-at value 0(1). To
propagate the effect of this fault to a circuit output one must sensitize at least one
path starting at line r to the circuit output by setting the side inputs of the gates in the
path to non-controlling values. This is illustrated in Fig. 3.2 where a test to detect
line f stuck-at-1 is shown. The fault on line f is activated by setting f to 0 in the
fault-free circuit and the fault is propagated to the output by setting the side inputs
k and g of the unique path from f to the circuit output to the non-controlling value
0. In order to obtain the desired values at the fault site and the side input values the
circuit inputs a, b, c, d and e must be set to the values shown in Fig. 3.2 . Also, in
Fig. 3.2 , the signal values shown as p/q are the composite values in the fault-free
and faulty circuit with the value above the slash, “/”, representing the signal value
in the fault-free circuit and below the slash the signal value in the faulty circuit. The
example in Fig. 3.2 also illustrates what are called necessary assignments (NA). For
example in order to activate the fault f stuck-at 1 line f has to be set to 0 which in
turn implies that inputs a and b must be set to 0. Similarly in order to propagate the
fault effect to the circuit output line k and g must be set to 0. In order to set line g to
0 inputs c and d must be set to 0. With input d set to 0 in order to set k to zero e must
be set to 1. The unique values needed to activate and propagate a fault are called
necessary assignments which can be obtained through what are known as forward
and backward (unique) implications ( Abramovici et al. 1990 ) and through what are
known as static and dynamic learning ( Schulz et al. 1988 ).
3.1.2
Delay Fault Models
Two basic fault models proposed in the literature to model defects that increase
circuit delays are gate delay faults ( Carter et al. 1987 ) and path delay faults
( Smith 1985 ). In gate delay fault model we associate with each circuit line a slow
to rise (STR) and a slow to fall (STF) fault and a size of the fault which is the ad-
ditional delay due to a defect added to the modeled delay for propagation of rising
 
 
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