Hardware Reference
In-Depth Information
g
a
m
q
p
k
s
b
c
r
n
h
d
u
t
e
f
Fig. 3.1
Illustrating some terms used
path we associate two logical paths one with a rising signal transition at the input to
the path and one with a falling transition at the input to the path. The circuit leads
on a path that are inputs to the gates on the path are called the on-path inputs and
the other inputs to the gates on the path are called the side inputs or off-path inputs.
a-m-p-q-s is a physical path with on-path inputs a, m, p and q and side inputs n, r and
the upper fan-out branches of k and p. Associated with the physical path a-m-p-q-s
we have two logical paths with rising and falling transitions at input a of the path.
Each logical path has a delay associated with it which is the sum of the delays on
the on-path circuit leads in the path.
In Fig.
3.1
the parts of the circuit enclosed by the dashed triangles are called fan-
out-free regions (FFRs). Given any combinational circuit one can uniquely partition
the circuit into FFRs. Inputs to a FFR are branches of fan-out stems or circuit inputs
without fan-out of >1 and the output of a FFR is either a fan-out stem or a circuit
output. For example the inputs to the FFR on the left of Fig.
3.1
are circuit inputs a
and d and the two fan-out branches of fan-out stem k. Note that from any input of
an FFR there is a unique physical path to the output of the FFR.
In order to detect a modeled fault two steps called fault activation and fault ef-
fect propagation are needed. For brevity, fault effect propagation is referred to as
fault propagation. Fault propagation requires sensitizing one or more circuit paths
or subpaths starting from the fault site to a circuit output. We say that a circuit path or
subpath is sensitized if the path/subpath output value changes when the path/subpath
input value changes (due to the fault effect). A circuit path/subpath is sensitized by
setting the side inputs of the gates along the path/subpath to specific values. Next
we illustrate these concepts for the most widely used fault model called the line
stuck-at fault model. We say that a line r in a faulty circuit is stuck-at-v, v
D
0 or
1, if line r is permanently at logic state v. If the circuit has N lines then the num-
ber of single line stuck-at faults is 2
N and hence the total number of faults to
be considered is linear in the size of the circuit. It is possible to reduce the total of
explicitly considered faults for test generation by collapsing the set of faults using
what are called fault equivalence and dominance relations
(
Abramovici et al.
1990
)
.
