Hardware Reference
In-Depth Information
a
b
R
b
V
A
V
B
V
O (AO3A)
D
C
AO3A
V
A
B
A
V
B
R
b
V
O (NAND2)
level and (
b
) transistor level
2.5
Summary
Traditional test techniques use the 'universal' stuck-at fault model to generate tests
that are expected to detect various types of real defects. In this context, the test
quality relies on detection of non-directly targeted defects. As the demand for high
quality test increases, the limitations of the stuck-at fault model to adequately rep-
resent and predict the behaviour of frequent realistic defects such as bridges and
opens, have demonstrated the need for more accurate and specific fault models. Un-
der such conditions, extensive research works have been devoted to the modeling,
detection and diagnosis of bridging defects.
The first models proposed for bridging defects were the so-called
wired models
which were inherited from previous non-CMOS technologies. Due to their intrinsic
limitations, they were rapidly replaced by the family of voting models. All these
models assume that the unpredictable resistance of the bridge is very small and can
be neglected. However it has been experimentally proved that the resistance of a
bridging defect is not small and has to be considered to understand its behaviour.
From these observations and considering the unpredictability of the resistance,
new concepts were proposed which take into account the range of resistance that can
be detected by a given vector: the Analogue Detectability Interval (ADI). Implemen-
tation of these new concepts into ATPG tools and Fault Simulators is described in a
following chapter.
It is well-known that defects can be detected using logic-based techniques as
well as current-based techniques. Indeed the quiescent current testing technique has
been widely used for the detection of bridging defects. The effectiveness of I
DDQ
has been reported in a wide range of works to detect various bridging defect classes.
I
DDQ
testing provides high defect observability but suffers from low test applica-
tion frequency and the presence of high background leakage currents in present
CMOS technologies. To improve the I
DDQ
test technique efficiency, refined tech-
niques have been developed such as the 'Delta I
DDQ
', current signature, current
