Models for Bridging Defects Test and Diagnosis - Models in Hardware Testing - page 54

namely: lowering test temperature, controlling the back vias voltages, partitioning
the device using multiple power sources, multiple transistors thresholds or Silicon
On Insulator (SOI) technologies for a sharper sub-threshold swing.

2.3.3.3 Very Low Voltage Testing

In case of bridges, different voltage-based techniques have been developed to im-
prove the observability of their effect on defective circuits. One of the most common
techniques is lowering the power supply voltage below the nominal operation value.
In fact, this technique has been demonstrated to detect defects which are not detected
by means of other testing techniques ( Hao and McCluskey 1993 ; Chang 1998 ; Mc-
Cluskey and Tseng 2000 ).
Different works reported the effectiveness of lowering the power supply voltage
in logic tests when detecting bridges. Very Low Voltage (VLV) logic testing is suit-
able in order to detect resistive bridges. Some works reported that lowering V DD
is appropriate to detect bridges (Engelke et al. 2004), since the critical resistance
(the highest bridging resistance which can be detected by means of logic tests) in-
creases as V DD decreases ( Kruseman et al. 2002 ). Chao-Wen et al. ( 2001 ) proposed
a different concept when lowering the power supply value based on the minimal
V DD . At a given clock frequency, this technique consists in lowering the V DD value
until obtaining the minimum V DD at which the device still functions. The authors
showed that some defective devices had a higher minimum V DD than the fault free
ones.
In general, lowering the power supply value is a technical condition easy to im-
plement, since it does not require any extra equipment or performance. However, it
decreases the speed of the circuit-under-test. Thus, there is an increase in test time
because the clock frequency is lower than the one at nominal conditions.

2.3.3.4 Shmoo Plots

Shmoo plotting analyzes the performance of a digital IC compared to the major
analogue parameters that influence the characteristics of the electrical behaviour
of the circuit (Baker and van Beers 1997). Shmoo plotting offers a way to visual-
ize the relationship between the performance of an IC and changes in the external
environment, such as temperature, V DD , and timing ( Huott et al. 2000 ; Chao-Wen
et al. 2001 ; Kruseman et al. 2002 ).
Figure 2.18 illustrates two Shmoo plots (V DD vs Period) for a combinational
CMOS circuit. As the example shown in this figure, given a working frequency
of the defective circuit, the majority of bridging defects allows the circuit to work
properly provided a sufficiently high V DD is applied. This is due to the fact that the
resistance of the connected n-network and p-network decreases with increasing V DD
making the effect of the (fixed) resistance of the bridge less visible. However, not
all the bridging defects cause the same type of shmoo plot. For two balanced n and