Hardware Reference
In-Depth Information
a
b
0
1
V A
R B
V B
I DDQ
I DDQ(defective)
V A
I DDQ
I DDQ(non-defective)
t
Fig. 2.14 Bridging defect affecting the output of an inverter at the ( a ) gate level and its ( b ) I DDQ
consumption versus the logic signal at the input of the defective gate
The effectiveness of I DDQ testing has been reported in a wide range of works
( Baschiera and Courtois 1984 ; Turner et al. 1985 ; Rodrıguez-Montanes et al. 1991 )
to detect different bridging defect classes, such as interconnect bridges, gate oxide
bridges and inter-gate bridges. Two bridged nodes set to the opposite logic value
create a current path between the power and ground rails ( Acken 1983 ) . Conse-
quently, an extra current above the defect-free case is generated flowing from power
to ground nodes. An example of the I DDQ testing technique applied to the detection
of bridging defects is illustrated in Fig. 2.14 , where an inverter contains a bridging
defect (R B ) between its output and the power node (or equivalently, between the
source and the drain of the pMOS transistor). When the inverter input (V A )isina
low logic state, the nMOS transistor is off. The current consumption is only due to
leakage current, as shown in Fig. 2.14 b . However, if V A transitions from logic 0 to
logic 1, the nMOS transistor turns on and the pMOS transistor turns off. In the fault
free case, once all the signals have settled-down, the current consumption is again
the leakage current. Nevertheless, due to the bridge, during the high logic state of
V A there is a current flowing from the power rail to ground through the nMOS tran-
sistor, increasing the quiescent current value.
I DDQ testing provides high defect observability. Indeed, it requires only fault
sensitization, since the fault-effect is always observable through the power supply
current measurement. Hence, the fault propagation requirement during test gener-
ation is not needed unlike logic based testing techniques. However, I DDQ testing
technique has some drawbacks ( Soden and Hawkins 1996 ; Sachdev 1997 ; Ferre
and Figueras 1997 ; Figueras and Ferre 1998 ) . Among them, it must be pinpointed
that it offers low test application times since it needs to wait for the level to settle
and then perform the sensing and the comparison of the current level with the test
threshold value. This drawback can be partially solved due to the lower required
number of vectors compared to the required in voltage based techniques.
The most important drawback is due to the shrinking of minimum feature size for
CMOS technology nodes. The theoretical basis of I DDQ consists in the appropriate
estimation of the leakage current for the defect-free circuit in order to determine the
threshold value above which the circuit will be considered defective. Due to statis-
tical variations of process parameters, the defect-free current consumption can not
 
 
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