Models for Bridging Defects Test and Diagnosis - Models in Hardware Testing - page 50

This example leads to the following key definition:

Definition 2.3. Given a circuit under test and the list of Analogue Detectability
Intervals ADI V associated to each possible input vector V for a considered defect,
optimizing the defect detection process consists in finding a minimum number of
input test vectors that cover the Global-ADI.

At this point, the problem is equivalent to any coverage problem and can be treated
by classical algorithms. Considering the simple example of Table 2.4 , it is clear here
that several minimum solutions exist. For instance, a test sequence composed of the
two vectors #6 and #7 covers the complete Global-ADI:

ADI D 0; R 2 C [ R 2 C ;R 4 C D 0; R 4 C D G ADI

C

It is worth highlighting that vector #7 appears as an 'essential' vector to cover the
Global-ADI whereas this vector would not be generated by a classical ATPG. In
other words, the detection of a bridge defect with a resistance falling into the interval
[R 2 C ,R 4 C ] is not guaranteed using the stuck-at fault model, while it exists some input
vectors (#7 and #11) able to detect the defect.

2.3.3 Alternative Detectability Techniques

Some of the alternative techniques to the logic-based detectability strategies are
presented in this subsection. Among them, the widely used detectability techniques
based on the surveillance of quiescent current consumption are reviewed in more
detail.

Quiescent Current (I DDQ / 2.3.3.1 Te s t i n g

At the early 1980s, an alternative testing technique for bridging and other defects in
CMOS technologies was proposed by Levi ( 1981 ). According to his proposal, the
increased testability of CMOS technologies is based on their negligible static cur-
rent consumption if no defect is present in the circuit. This characteristic is derived
from the complementary nature of the n-network versus the p-network that avoids
the simultaneous conduction of both networks provided a quiescent state has been
reached.
The quiescent current (I DDQ ) testing technique ( Malaya and Su 1982 ) has been
widely used for the detection of bridging faults. It is based on the fact that the defect
causes an increase in the quiescent current consumption of the circuit provided the
appropriate excitation is applied. It consists in monitoring the power supply current
(I DDQ ) once all the transient currents in the circuit have settled-down. The measured
current is compared to a threshold value and if it is higher than this reference current,
the device is considered faulty.