Hardware Reference
In-Depth Information
I
2
= 0
I
1
= 0
Gate c
Vn
1
n
3
= effect
Gate a
Vth
c
1
Gate e
Rsh
O = effect
0
Gate d
I
3
= 1
Gate b
Vth
d
n
2
0
n
4
= effect
I
4
= 1
Vn
1
5
Vth
d
#3
Vth
c
#2
0
R
1
C
R
3
C
Rsh
Fig. 2.12
Different propagations
(
Renovell et al.
1999
)
Vn
1
5
Vth
d
Vth
c
0
Rsh
5
Vn
3
Vn
4
0
Rsh
O
5
Defect
free
Defective
Defect
free
0
R
1
C
R
3
C
Rsh
This small example also points out that classical fault propagation procedures
used in ATPG are inappropriate to handle non-zero resistance bridging defects.
Indeed, a classical ATPG would allow fault propagation only through gate 'c' as
