Hardware Reference
In-Depth Information
Tabl e 2. 3 Defect excitation
and propagation ( Renovell
et al. 1999 )
#
I 1 I 2 I 3 I 4
Excitation
Propagation
0
0000
Y
N
1
0001
Y
N
2
0010
Y
Y
3
0011
Y
Y
4
0100
Y
N
5
0101
Y
N
6
0110
Y
Y
7
0111
Y
Y
8
1000
Y
N
9
1001
Y
N
10
1010
Y
Y
11
1011
Y
Y
12
1100
N
N
13
1101
N
N
14
1110
N
Y
15
1111
N
Y
I 1 = 0
I 2 = 0
Gate c
Vn 1
n 3 = effect
Gate a
1
Gate e
Rsh
O = effect
0
Gate d
I 3 = 1
Gate b
n 2
1
n 4
I 4 = 0
Fig. 2.9
Effect of the defect ( Renovell et al. 1999 )
a bridge resistance are under consideration. Indeed, an excited defect can produce
either a defective effect or a defect-free effect depending on the bridge resistance
value Rsh, which is evidently an unpredictable parameter. For this reason, we refer
to “effect” propagation.
To illustrate this point, let us consider the circuit of Fig. 2.8 with vector #2 on
its inputs. This vector guarantees both defect excitation and effect propagation. In
Fig. 2.9 , only the 'ON' transistors of the NAND gate 'a' are represented.
Vector #2 tries to set node n 1 to a logic '1'. Under such conditions, a conducting
path is created from Vdd to Gnd through node n 1 including the resistance Rsh of the
defect. An intermediate voltage Vn 1 appears on node n 1 . The logic interpretation of
this intermediate voltage depends on the logic threshold Vth c of the driven NAND
gate 'c':
 
 
 
 
Search WWH ::




Custom Search