Hardware Reference
In-Depth Information
model evaluates the relative strengths of the different networks by means of SPICE
simulations, which are stored in tables. During fault simulation, this information is
accessible and no SPICE simulations are required. In a first approach, the model
assumes that all the downstream gates have the same threshold. However, the same
authors refined this fact in
Acken and Millman
(
1992
)
. The limitation of this fault
model is that if any new logic element has a threshold voltage outside the range used
to generate the tables, new simulations are required. Furthermore, results when the
strengths of the pMOS and nMOS networks are similar are not accurate. To over-
come the limitations of the voting model, an improved fault model was proposed by
Maxwell and Aitken
(
1993
) the biased voting model. In this case, the threshold volt-
age is not considered fixed. The biased voting model is able to calculate the voltage
values of the bridged nets by means of an iterative procedure.
The biased voting model allows to perform fault simulation at the logic level us-
ing electrical information obtained through an electrical pre-characterization of the
library. However, the fault simulation is considerably slowed down by the iterative
procedure requested to precisely compute the effective voltage value Vx. The objec-
tive of the direct-voting model proposed later by
Renovell et al.
(
1994a
)
is to keep
the same accuracy as the biased-voting model while removing the iterative proce-
dure. The direct-voting model allows to get the voltage values Vx directly without
any computation or iteration.
The fundamental concept of the direct voting model is very simple and comes
from a very simple observation:
1.
Assuming a bridging defect between two logic nodes set to opposite logic values,
the resulting intermediate voltage Vx could be computed as a function of the
topological parameters of the p-transistors (W
p
,L
p
) and n-transistors (W
n
,L
n
),
plus the technological parameters such as C
ox
,
n
,
p
,V
Tn
,V
Tp
:::
2.
For the different possible bridging defects in a given circuit, all the technological
parameters are the same.
As a consequence, for a given circuit with known technological parameters, the
resulting intermediate voltage Vx of a bridging defect is only a function of the topo-
logical parameters of the bridged p- and n- ON transistors and, more precisely, of
the so-called configuration ratio “:
Vx
D
f.“/ with “
D
W
p
=L
p
=.W
n
=L
n
/
The authors proposed to perform a pre-characterization of the library by drawing
the Vx versus “ characteristics using SPICE simulations. Note that these charac-
teristics are constructed and memorized for different parallel and serial networks
of transistors. During fault simulation, the fault simulator knowing the topological
parameters and so knowing the configuration ratio of the bridged gates, can directly
deduce from the above characteristics the voltage value Vx without any computation
or iteration.
Other works tried to develop more accurate fault models.
Rearick and Patel
(
1993
) presented a fault model where the use of SPICE-derived data for every input
