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a
b
c
V A
V A
V A
R b
V B
V B
V B
Fig. 2.1
Two NAND gates. ( a ) Bridging fault, ( b ) wired-AND, and ( c )wired-OR
a
b
V A
V B
V A
V B
R b
R b
Fig. 2.2 Transistor description of a bridging fault between two NAND gates. ( a ) One pMOS
transistor on and ( b ) both pMOS transistors on
models assume. These fault models are more suitable for technologies where one
of the logic levels is clearly stronger than the other one. However, the wired-AND
and wired-OR fault models are the easiest for simulation, pattern generation and
diagnosis purposes.
2.2.2
The Voting Model and Other Zero Resistance Defect Models
A refinement of the wired-AND and the wired-OR fault models was subsequently
presented by Acken and Millman ( 1991 ) , the voting model . When the bridged nets
are set to opposite logic values, the voting model considers the resultant circuit as
a resistive divider between V DD and RV GND . In CMOS circuits, the electrical resis-
tance to V DD comes from a combination of conducting pMOS transistors, whereas
the resistance to V GND comes from a combination of conducting nMOS transistors.
The voting model also assumes that the bridge resistance is negligible. The evalua-
tion of the two networks strengths determines whether the net is considered as logic
1 or logic 0. Nevertheless, this fault model does not determine the actual values on
the bridged nets.
Considering the transistor description of the bridge between the outputs of two
2-input NAND gates illustrated in Fig. 2.2 , the voting model differentiates between
the strengths of the pMOS networks depending on the number of conducting pMOS
transistors to determine the logic interpretation of the bridged nets. The voting
 
 
 
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