Models for Bridging Defects Test and Diagnosis - Models in Hardware Testing - page 33

and CPU time limit test generation and application, generating tests for all defects
is unfeasible. Consequently, a relatively small set of abstract defects, namely faults,
is constructed and these faults are targeted to generate tests. With this approach, the
test quality relies on detection of non-directly targeted defects.
In this chapter, we consider a very frequent defect encountered in today technolo-
gies: the undesired electrical connection between adjacent lines known as bridging
defect . The advent of nanometer technologies with extensive interconnect structures
contributes to the need of effective models for this defect.
Defects originated in the manufacturing process must be tested and detected be-
fore the chip is mounted in the application. In many cases as for example systematic
defects, the defect has not only to be detected but also to be localized and identified.
For this reason, test but also diagnosis are two major factors of the final product
quality. Consequently, diagnosis techniques targeting bridging defects are also pre-
sented in this chapter.

2.2 Previous Work

The limitations of the Stuck-At fault model to adequately predict the behaviour of
frequent realistic defects such as bridges and opens have triggered active research
in the area since the 1970s. In this section, we analyze the evolution of the models
for bridges highlighting some of the key contributions.

2.2.1 Wired-AND and Wired-OR Models

This popular model assumes a logic value at the defective bridged nodes generated
by the AND or the OR function of the bridged nodes. A pioneering work on wired
bridging fault models was reported by Mei ( 1974 ) . These bridging fault models
are known as the wired-AND and the wired-OR bridging fault models. In a bridging
fault, each signal net tries to drive the bridged nets to a value equal to the logic value
in the fault-free circuit. The wired-AND and the wired-OR fault models assume
that the values on the bridged nets are both the same (zero bridge resistance) and
are the result of an AND or an OR operation between the logic values of the nets,
respectively.
Figure 2.1 shows an example of a bridge between the outputs of two NAND gates
and their equivalent wired-AND and wired-OR fault models. On the one hand, the
wired-AND fault model assumes that the nMOS transistor networks logically win
and drive the bridged nets when they are excited. On the other hand, the wired-OR
fault model considers that the pMOS transistor networks logically win when they
are excited. These fault models, although widely used in the past, do not reflect
the behaviour of bridging faults in CMOS technologies. The voltage on the bridged
nets is not always logic 0 or logic 1, as the wired-AND and the wired-OR fault