Models for Bridging Defects Test and Diagnosis - Models in Hardware Testing - page 32

Chapter 2
Models for Bridging Defects
Test and Diagnosis

Michel Renovell, Florence Azais, Joan Figueras, Rosa Rodrıguez-Monta nes,
and Daniel Arumı

Abstract Bridging defects are responsible for a large percentage of failures in
CMOS technologies and their impact in nanometer technologies with highly dense
interconnect structures is expected to increase. In this chapter, a survey of the key
developments in modeling bridging defects and their implications in test and diag-
nosis are presented. An overview of the historical developments of these models
from the “wired AND/OR” and “voting” models to more realistic proposals taking
into consideration the resistance values of the bridge are presented. The logic de-
tectability of bridging defects considering the resistance of the bridge assuring its
detectability is explored. The concept of Analogue Detectability Interval (ADI) as
well as its applicability to increase the quality of the vectors detecting these de-
fect classes is introduced. Quality of electronic circuits and systems requires the
availability of effective diagnosis techniques. The basic concepts of logic as well as
current-based (I DDQ ) diagnostic strategies are included in this chapter.

Keywords VLSI Test Diagnosis Defect Short Bridging defect CMOS

Realistic model Analogue detectability interval

2.1 Introduction

Traditionally, test generation relies on fault models to produce tests that are expected
to identify defects such as unintended bridges and opens. Test generation does not
directly target defects for two main reasons. Firstly, many defects are not easy to
analyze and no model exists to completely describe their behaviour. Secondly, there
is a variety of possible defects in a circuit. Since available resources (like memory)

) and F. Azais
LIRMM-CNRS, 161 rue ada, 34392 Montpellier, France
e-mail: [e-mail] , [e-mail]
J. Figueras, R. Rodrıguez-Monta nes, and D. Arumı
Universitat Politecnica de Catalunya (UPC), Electronic Engineering Dpt. ETSEIB,
Diagonal 647, 08028 Barcelona, Spain
e-mail: [e-mail] , [e-mail] , [e-mail]

M. Renovell (