Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 27

predicted voltage of the floating line for the dotted patterns must be above those for
the plain patterns. Note that the methodology is based on relative predictions of the
floating line. Thus, uncertainty due to the trapped charge and the threshold voltage
of the downstream gate is eliminated. The predictions in Fig. 1.25 a are consistent
for two ranges of locations (A and B). The rest of locations can be discarded.
Based on the same methodology, the authors also proposed, when feasible, the
use of I DDQ measurements to improve the accuracy of diagnosis results. The pre-
dictions of the floating line voltage allowed, in turn, the extra current consumed by
the downstream gate to be predicted by SPICE simulations. The predicted currents
were compared with the results obtained from the I DDQ test, and the correlation co-
efficient between the predicted and measured currents was calculated. Results for
the same defective device are shown in Fig. 1.25 b . By combining both logic and
current results, the authors determined that the most likely location for the open is
region A (at the beginning of the defective net, close to the driver).
Liu et al. ( 2007 ) presented a diagnosis methodology minimizing the layout in-
formation to locate open vias. Depending on the interpretation of the floating line
voltage, one of the following equations must be satisfied:

C 1 .P /
C TOT

V FL .P / D V DD C V Qo >V th .P /

C 1 .P /
C TOT

V FL .P / D V DD C V Qo <V th .P / (1.13)

where C 1 .P/ is defined as in Eq. 1.9 . Considering that C 1 .P/ is pattern dependent,
it is possible to rearrange the previous inequalities in the following way:

C a1 .P /V DD C k V th .P /C tot >0

C a1 .P /V DD C k V th .P /C tot <0 (1.14)

C a1 .P/ is the part of C 1 .P/ referring to the neighboring coupling capacitances tied
to logic 1 for pattern P, and k is a pattern independent variable depending on Q o and
other known variables. These inequalities are linear. Hence, for every applied test
pattern, an inequality like those in Eq. 1.14 is obtained. Then, given n test patterns,
n inequalities are reported. A solver can be used to determine if these inequalities
have a solution. If not, the suspected via is removed from the list.
Little research has addressed the diagnosis of resistive open defects since these
are intrinsically included in methodologies for delay fault diagnosis. However,
James and McCluskey ( 2005 ) proposed a methodology focused on the diagnosis
of resistive opens, in particular based on the transition fault model. Transition faults
are timing failures large enough to make the path delay through which the fault is
propagated exceed the clock interval. Figure 1.26 shows the fourteen possible re-
sistive open locations in a NAND gate. The eleven intra-gate resistive open defects
.R 1 -R 11 / can be modeled as single-transition faults. The inter-gate resistive open
defects .R 12 -R 14 / cannot be modeled as any single-transition fault. They must be