Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 21

1.3.2 Detectability of Intra-gate Open Defects

Early research to detect intra-gate open defects was founded on logic-based tech-
niques. Nevertheless, these cannot always ensure the detectability of such opens.
Logic based techniques and alternatives are presented in this section.

1.3.2.1 Logic Detectability of Intra-gate Open Defects

As already seen in Section 1.2.2 , the detectability of stuck open faults depends on
the pattern order. The output of the defective gate is in a high impedance state for
at least one input combination. In this situation, the output voltage depends on the
state induced by previous patterns. Therefore, with the appropriate pattern order,
logic testing is suitable for the detection of such defects ( Wadsack 1978 ; Soden
et al. 1989 ) .
If an open causes a single floating gate, its detectability depends on several fac-
tors ( Champac et al. 1993 , 1994 ; Ivanov et al. 2001 ), namely topological parameters,

trapped charge and unpredictable poly-to-bulk capacitance C pb . The detectability
of the fault can be ensured depending on the C pb value. The final value of the out-
put voltage of the affected gate increases with C pb . Therefore, a critical value of
the unpredictable parameter C pb can be defined to detect a single floating gate. The
detectability interval is defined as the range of C pd values where the open fault can
be detected.

1.3.2.2 Delay Detectability of Intra-gate Open Defects

Like interconnect resistive opens, intra-gate resistive opens influence the transient
behavior of defective devices. In general, the higher the resistance, the larger the
delay. Furthermore, the exact location of the intra-gate resistive open also has a
significant impact on the transient behavior of the affected circuit, as analyzed by
Baker et al. ( 1999 ). This work considered a 0:25 m standard cell library. Transistor
level netlists and interconnect parasitics were extracted from layout to find the criti-
cal resistances. For resistive drain/source faults, simulation results showed that most
critical resistances were about 50 k. However, for resistive single transistor gate
faults, critical resistances ranged between M and a few tens of M depending on
the duty cycle of the input waveform.
In some cases, time considerations can also be useful in the detectability of
intra-gate full open defects. For single floating nMOS (pMOS) transistors, a ris-
ing (falling) transition applied to the defective input may detect the presence of such
faults provided that the delay is large enough to generate a fault ( Ivanov et al. 2001 ) .
This delay depends on topological parameters and C pb . In general, the higher C pb ,
the larger the delay.